In general, the design of digital integrated circuits includes two main design phases such as, for example, an RTL (register transfer level) design phase and a physical design phase. An RTL design phase is performed by converting a user specification of chip function into an RTL description, which specifies how each portion of the chip operates on each clock cycle. In the physical design phase, a chip design is generated using a corresponding RTL file and a library of standard component cells such as basic logic gates (AND gate, OR gates, NAND gates, NOR gates, etc.) and macro cells such as adders, multiplexers, flip-flops, memory, etc. More specifically, a physical design phase includes various phases such as logic synthesis, placement, clock-tree synthesis, and routing.
With present technologies, each of the physical design flow steps of logic synthesis, placement, clock-tree synthesis, and routing need to be timing-aware in order for a given design to properly meet specified timing constraints/requirements. Timing closure is a process by which a chip design is iteratively modified to meet specified timing constraints/requirements. Timing closure requires a balancing of data delays and clock delays with the given timing constraints/requirements. Typically, integrated circuit (IC) chip designers will attempt to close timing at all stages of the physical design process such as placement, clock tree synthesis, and routing. A chip designer may rely on changes in clock latency to close timing without disturbing data paths. For example, if the clock latency to a given macro cell is determined to be unacceptable, the chip designer must rebuild an associated clock-tree network. Once a clock-tree network is built, however, it is very challenging to change clock delays or data delays because any change that is made to the clock-tree network after the routing process is complete can affect other non-related paths. If the latencies are not correct, various design steps such as placement, clock tree synthesis, and routing must be repeatedly performed to meet the required timing constraints/requirements, which can be extremely time consuming and costly in terms of engineering hours.